EDS Characterisation of the SRAM device

Aim

The rise of emerging industries, such as 5G and artificial intelligence, has increased requirements for memory devices, such as Static Random-Access Memory (SRAM) (e.g. increased storage density, higher read and write speeds and greater reliability). In order to achieve the necessary performance, devices must be characterised to ensure that they have been manufactured correctly and to investigate any failures.

Challenge

Interconnects play a critical role in high performance memory devices. Copper (Cu) is widely used due to its low bulk resistivity and high electrical reliability; however, multiple layers of different specification are often required. As device miniaturisation proceeds ever further, characterising all aspects of these device components becomes increasingly challenging.

Solution

High-resolution EDS mapping of bulk devices using Ultim Extreme can be employed for the examination of the interface between the metal and dielectric layers which are critical parts in many electronic devices. The same setup can also be used for diffusion tracking of metallic species and the assessment of the "critical" thickness of the barrier layers.

Results

Figure 1 shows a Cu-Damascene interconnect. The blue colour in Figure 1(c) shows the distribution of TaN, which is deposited between the Cu interconnect and the dielectric layer shown in orange. It is only 10 nm in thickness and perfectly matches the electron image in Figure 1(b). In order to prevent the dielectric layer from being damaged during processing and to prevent moisture absorption from the environment, a dielectric barrier layer needs to be protectively plated. In this case, a Si₃N₄ dielectric barrier layer is shown in green above the metal layer. It is even possible to spot dielectric layer doping with F, shown in purple. Electromigration of Cu hasn't been observed here. All interconnects are isolated by fluorosilicate/phosphosilicate glass.

Conclusion

It is not adequate to solely rely on electron images to check device structure, as it can be difficult to observe the distribution of the barrier, dielectric layers and dopant regions. This makes high-resolution EDS analysis with Ultim Extreme indispensable in semiconductor applications. It provides a means for the characterisation of multiple interfaces at a nm scale and also enables the operator to check that the device meets requirements such as the need for electromigration-redundant Cu interconnects, as required in high performance memory devices.